LPV542 Datasheet, PDF (5/29 Pages) Texas Instruments – LPV542 Dual Nanopower 1.8 V, 490nA, RRIO CMOS Operational Amplifier

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6.5 Electrical Characteristics 1.8 V
T_A = 25°C, V⁺ = 1.8V, V^− = 0V, V_CM = V_O = V⁺/2, and R_L > 1 MΩ , unless otherwise noted.
PARAMETER
TEST CONDITIONS
OFFSET VOLTAGE
Input offset voltage (V_OS)
Over temperature
Drift (dV_OS/dT)
Power-Supply Rejection Ratio
(PSRR)
V_CM = 0.3 V
V_CM = 1.5 V
V_CM = 0.3 V and 1.5 V
V_S = 1.6 V to 5.5 V, V_CM = 0.3 V
INPUT VOLTAGE RANGE
Common-mode voltage range (V_CM)
Common-Mode Rejection Ratio
(CMRR)
INPUT BIAS CURRENT
CMRR ≥ 60 dB
0 V < V_CM < 1.8 V
0 V < V_CM < 0.7 V
1.3 V < V_CM < 1.8 V
Input bias current (I_B)
Input offset current (I_OS)
INPUT IMPEDANCE
T_A = 25°C
T_A = –40°C to 125°C
Differential
Common mode
NOISE
Input voltage noise density, f = 1 kHz (e_n)
Current noise density, f = 1 kHz (i_n)
OPEN-LOOP GAIN
Open-loop voltage gain (A_OL)
OUTPUT
Voltage output swing from positive rail
Voltage output swing from negative rail
Output current sourcing
Output current sinking
FREQUENCY RESPONSE
R_L = 100 kΩ to V⁺/2, 0.5 V < V_O < 1.3 V
R_L = 100 kΩ to V⁺/2
R_L = 100 kΩ to V⁺/2
Sourcing, V_O to V^–, V_IN(diff) = 100 mV
Sinking, V_O to V⁺, V_IN(diff) = –100 mV
Gain-bandwidth product (GBWP)
Slew rate (SR)
POWER SUPPLY
C_L = 20 pF
G = +1, Rising edge, 1V_p-p, C_L = 20 pF
G = +1, Falling edge, 1V_p-p, C_L = 20 pF
Specified voltage range (V_S)
Quiescent current per channel (I_Q)
Over temperature
V_CM = 0.3 V, I_O = 0
Quiescent current per channel (I_Q)
Over temperature
V_CM = 1.5 V, I_O = 0
(1) Refer to Typical Characteristics.
LPV542
SNOSCX9 – MARCH 2015
MIN TYP⁽¹⁾ MAX UNIT
±1
±1
1
83
109
±2
±3 mV
±4
µV/°C
dB
0
1.8 V
63
92
87
92
dB
63
98
±0.1
±1
±100 pA
±0.1
±1
10¹³ || 2.5
10¹³ || 2.5
Ω || pF
250
nV/√Hz
80
fA√Hz
91
101
dB
3
20
mV
2
20
1
3
mA
1
5
7
kHz
3.4
V/ms
3.7
1.6
5.5 V
490
800
1100
nA
680 1100
1500
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