LPV542 Datasheet, PDF (15/29 Pages) Texas Instruments – LPV542 Dual Nanopower 1.8 V, 490nA, RRIO CMOS Operational Amplifier

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LPV542
SNOSCX9 – MARCH 2015
Device Functional Modes (continued)
For the lowest supply current operation, keep the input common mode range between V- and 1 V below V+.
7.4.3 Design Optimization With Rail-To-Rail Input
In most applications, operation is within the range of only one differential pair. However, some applications can
subject the amplifier to a common-mode signal in the transition region. Under this condition, the inherent
mismatch between the two differential pairs may lead to degradation of the CMRR and THD. The unity-gain
buffer configuration is the most problematic as it will traverse through the transition region if a sufficiently wide
input swing is required.
7.4.4 Design Optimization for Nanopower Operation
When designing for ultralow power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors will react with stray capacitance in the circuit and the input capacitance
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. A
feedback capacitor may be required to assure stability and limit overshoot or gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors since large electolytics may have static leakage currents in the tens to hundreds
of nanoamps.
7.4.5 Common-Mode Rejection
The CMRR for the LPV542 is specified in two ways so the best match for a given application may be used. First,
the CMRR of the device in the common-mode range below the transition region (V_CM < (V+) – 0.9 V) is given.
This specification is the best indicator of the capability of the device when the application requires use of one of
the differential input pairs. Second, the CMRR at V_S = 5 V over the entire common-mode range is specified.
7.4.6 Output Stage
The LPV542 output voltage swings 3 mV from rails at 3.3 V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV542 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load.
7.4.7 Driving Capacitive Load
The LPV542 is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be under damped which causes peaking in the transfer and, when there is too much peaking, the
op amp might start oscillating.
In order to drive heavy (>50pF) capacitive loads, an isolation resistor, R_ISO, should be used, as shown in
Figure 38. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger
the value of R_ISO, the more stable the amplifier will be. If the value of R_ISO is sufficiently large, the feedback loop
will be stable, independent of the value of C_L. However, larger values of R_ISO result in reduced output swing and
reduced output current drive.
-
V_IN
+
R_ISO
C_L
V_OUT
Figure 38. Resistive Isolation Of Capacitive Load
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