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| DAC8550_15 Datasheet, PDF (5/28 Pages) Texas Instruments – 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | |||
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www.ti.com
SERIAL WRITE OPERATION
SCLK
SYNC
DIN
1
t8
t4
t3
DB23
t6
t5
t1
24
t2
t7
DB0
DAC8550
SLAS476E â MARCH 2006 â REVISED MARCH 2012
t9
DB23
TIMING CHARACTERISTICS(1) (2)
VDD = 2.7V to 5.5V, all specifications â40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
t1 (3) SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4 SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7 24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9 24th SCLK falling edge to SYNC falling edge
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VDD = 3.6V to 5.5V
VDD = 2.7V to 5.5V
MIN
50
33
13
13
22.5
13
0
0
5
5
4.5
4.5
0
0
50
33
100
TYP MAX
(1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation Timing Diagram.
(3) Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2006â2012, Texas Instruments Incorporated
Product Folder Link(s): DAC8550
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