DAC8550_15 Datasheet, PDF (15/28 Pages) Texas Instruments – 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

DAC8550
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THEORY OF OPERATION
SLAS476E – MARCH 2006 – REVISED MARCH 2012
DAC SECTION
The architecture of the DAC8850 consists of a string
DAC followed by an output buffer amplifier. Figure 45
shows the block diagram of the DAC architecture.
DAC
Register
V_REF
50kW
62kW
REF(+)
Resistor String
REF(-)
GND
50kW
V_FB
V_OUT
R
R
R
To Output
Amplifier
Figure 45. DAC8550 Architecture
The input coding to the DAC8550 is 2's complement,
so the ideal output voltage is given by:
V _OUT
+
V_REF
2
)
V_REF D
65536
(1)
where D = decimal equivalent of the 2's complement
code that is loaded to the DAC register; D ranges
from –32768 to +32767 where D = 0 is centered at
V_REF/2.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
Monotonicity is ensured because of the string resistor
architecture.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail output voltages with a range of 0V to V_DD. It
is capable of driving a load of 2kΩ in parallel with
1000pF to GND. The source and sink capabilities of
the output amplifier can be seen in the Typical
Characteristics. The slew rate is 1.8V/μs with a full-
scale setting time of 8μs with the output unloaded.
The inverting input of the output amplifier is brought
out to the V_FB pin. This architecture allows for better
accuracy in critical applications by tying the V_FB point
and the amplifier output together directly at the load.
Other signal conditioning circuitry may also be
connected between these points for specific
applications.
R
R
Figure 46. Resistor String
SERIAL INTERFACE
The DAC8550 has a 3-wire serial interface (SYNC,
SCLK, and D_IN), which is compatible with SPI, QSPI,
and Microwire interface standards, as well as most
DSP interfaces. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line
LOW. Data from the D_IN line are clocked into the 24-
bit shift register on each falling edge of SCLK. The
serial clock frequency can be as high as 30MHz,
making the DAC8550 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock, the
last data bit is clocked in and the programmed
function is excuted (that is, a change in DAC register
contents and/or a change in the mode of operation).
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. Since the SYNC buffer
draws more current when the SYNC signal is HIGH
Copyright © 2006–2012, Texas Instruments Incorporated
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