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| CDCDLP223_07 Datasheet, PDF (5/9 Pages) Texas Instruments – 3.3 V Clock Synthesizer for DLP Systems | |||
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www.ti.com
APPLICATION INFORMATION
CDCDLP223
SCAS836 â DECEMBER 2006
Figure 1. Timing Diagram, Serial Control Interface
3.3V
20MHz
SCLK
SDATA
ID0
EN
3.3V
100MHz
2
Spread
IREF
CDCDLP223
320MHz 20MHz
2
CDCD5704 ISET
400MHz
2
Spread
ID1 ID0
Spread No Spread
XDR
DRAM
Clock
Distribution
DMD
PLL
Control
xN
Logic
DLPTM Processor Chip
XD?iv by A
XD?iv by B
XD?iv by C
.
.
.
ClockA
ClockB
ClockC
Figure 2. Typical CDCDLP223 Application
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