CDCDLP223_07 Datasheet, PDF (4/9 Pages) Texas Instruments – 3.3 V Clock Synthesizer for DLP Systems

CDCDLP223
SCAS836 – DECEMBER 2006
TIMING REQUIREMENTS⁽¹⁾
over recommended ranges of supply voltage, load and operating free air temperature
PARAMETER
XIN, XOUT REQUIREMENTS
f_XIN
Frequency of crystal attached to XIN, XOUT, with C_L = 20 pF (2 × 40 pF) on-die
capacitance
2 WIRE SERIAL INTERFACE REQUIREMENTS STANDARD MODE
f_SCLK
SCLK frequency
t_h(START) START hold time (see Figure 1)
t_w(SCLL)
SCLK low-pulse duration (see Figure 1)
t_w(SCLH) SCLK high-pulse duration (see Figure 1)
t_su(START) START setup time (see Figure 1)
t_h(SDATA) SDATA hold time (see Figure 1)
t_su(SDATA) SDATA setup time (see Figure 1)
t_r(SDATA) SCLK / SDATA input rise time (see Figure 1)
t_f(SDATA) SCLK / SDATA input fall time (see Figure 1)
t_su(STOP) STOP setup time (see Figure 1)
t_BUS
Bus free time
2 WIRE SERIAL INTERFACE REQUIREMENTS FAST MODE
f_SCLK
t_h(START)
t_w(SCLL)
t_w(SCLH)
t_su(START)
t_h(SDATA)
t_su(DATA)
t_r(SDATA)
t_f(SDATA)
t_su(STOP)
t_BUS
SCLK frequency
START hold time (see Figure 1)
SCLK low-pulse duration (see Figure 1)
SCLK high-pulse duration (see Figure 1)
START setup time (see Figure 1)
SDATA hold time (see Figure 1)
SDATA setup time (see Figure 1)
SCLK / SDATA input rise time (see Figure 1)
SCLK / SDATA input fall time (see Figure 1)
STOP setup time (see Figure 1)
Bus free time
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MIN TYP MAX UNIT
20
MHz
0
100 kHz
4.0
µs
4.7
µs
4.0
µs
4.7
µs
0
3.45 µs
250
ns
1000 ns
300 ns
4.0
µs
4.7
µs
0
400 kHz
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
0.9 µs
100
ns
20
300 ns
20
300 ns
0.6
µs
1.3
µs
(1) The CDCDLP223 2-wire serial interface in Send-Mode meets both I²C and SMBus set up time t_su and hold time t_h requirements.
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