CDCDLP223_07 Datasheet, PDF (1/9 Pages) Texas Instruments – 3.3 V Clock Synthesizer for DLP Systems

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3.3 V Clock Synthesizer for DLP™ Systems
CDCDLP223
SCAS836 – DECEMBER 2006
FEATURES
• High-Performance Clock Synthesizer
• Uses a 20 MHz Crystal Input to Generate
Multiple Output Frequencies
• Integrated Load Capacitance for 20 MHz
Oscillator Reducing System Cost
• All PLL Loop Filter Components are
Integrated
• Generates the Following Clocks:
– REF CLK 20 MHz (Buffered)
– XCG CLK 100 MHz With SSC
– DMD CLK 200-400 MHz With Selectable
SSC
• Very Low Period Jitter Characteristic:
– ±100 ps at 20 MHz Output
– ±75 ps at 100 MHz and 200–400 MHz
Outputs
• Includes Spread-Spectrum Clocking (SSC),
With Down Spread for 100 MHz and Center
Spread for 200–400 MHz
• HCLK Differential Outputs for the 100 MHz
and the 200–400 MHz Clock
• Operates From Single 3.3-V Supply
• Packaged in TSSOP20
• Characterized for the Industrial Temperature
Range -40°C to 85°C
• ESD Protection Exceeds JESD22
• 2000-V Human-Body Model (A114-C) –
MIL-STD-883, Method 3015
TYPICAL APPLICATIONS
• Central Clock Generator for DLP™ Systems
DESCRIPTION
The CDCDLP223 is a PLL-based high performance
clock synthesizer that is optimized for use in DLP™
systems. It uses a 20 MHz crystal to generate the
fundamental frequency and derives the frequencies
for the 100 MHz HCLK and the 300 MHz HCLK
output. Further, the CDCDLP223 generates a
buffered copy of the 20 MHz Crystal Oscillator
Frequency at the 20 MHz output terminal.
CDCDLP223 PIN ASSIGNMENTS
XIN
XOUT
VSS
VDD
20MHZ
VSS
EN
IDO
SDATA
SCLK
1 ^{TSSOP 20} 20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
IREF
VDD
100MHZ
100MHZ
VSS
VSS
300MHZ
300MHZ
VSS
VDD
The 100 MHz HCLK output provides the reference
clock for the XDR Clock Generator (CDCD5704).
Spread-spectrum clocking with 0.5% down spread,
which reduces Electro Magnetic Interference (EMI),
is applied in the default configuration. The
spread-spectrum clocking (SSC) is turned on and off
via the serial control interface.
The 300 MHz HCLK output provides a 200-400 MHz
clock signal for the DMD Control Logic of the DLP™
Control ASIC. Frequency selection in 20 MHz steps
is possible via the serial control interface.
Spread-spectrum clocking with ±1.0% or ±1.5%
center spread is applied, which can be disabled via
the serial control interface
The CDCDLP223 features a fail safe start-up circuit,
which enables the PLLs only if a sufficient supply
voltage is applied and a stable oscillation is delivered
from the crystal oscillator. After the crystal start-up
time and the PLL stabilization time, all outputs are
ready for use.
The CDCDLP223 works from a single 3.3-V supply
and is characterized for operation from –40°C to
85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated