CDCDLP223_07 Datasheet, PDF (2/9 Pages) Texas Instruments – 3.3 V Clock Synthesizer for DLP Systems

CDCDLP223
SCAS836 – DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
XOUT
XIN
Crystal
Oscillator
20 Mhz
www.ti.com
LVTTL
20 Mhz
SSC PLL 1
OUT = 100 Mhz
–0.5% SSC
HCLK out
100 Mhz
VDD
150 KW
EN
SCLK
SDATA
2-Wire Serial
Interface
Control
Logic
IDO
SSC PLL 2
OUT = 200-400 Mhz
±1.0% and
±1.5% SSC
VDD
150 KW
VDD
VSS
HCLK out
300 Mhz
IREF
TERMINAL
XIN
XOUT
SDATA
SCLK
20 MHz
100 MHz
100 MHz
300 MHz
300 MHz
VDD
VSS
IREF
EN
IDO
TERMINAL FUNCTIONS
PIN
1
2
9
10
5
18
17
14
13
4,11,19
3,6,12,15,16
20
7
8
TYPE
DESCRIPTION
I
Crystal oscillator input for 20-MHz crystal in parallel resonance
O
Crystal oscillator output for 20-MHz crystal in parallel resonance
I/O Open drain Data I/O, 2-wire serial interface controller, internal 1-MΩ pullup
I Interface Clock Clock input, 2-wire serial interface controller, internal 1-MΩ pullup
O LVTTL Clock output, 20 MHz (buffered output from crystal oscillator)
O HCLK Clock output for XDR clock generator
O HCLK Clock output for XDR clock generator
O HCLK Clock output for DMD system
O HCLK Clock output for DMD system
Power
3.3 V Power supply
Ground
Ground
O R_REF to GND IREF pin for HCLK output drive-current biasing
I LVTTL
Output enable, 20 MHz, 100 MHz and 200–400 MHz outputs, 150 kΩ pullup, default =
logic high
I LVTTL
Sets 2-wire serial interface ID address bit A0, 150 kΩ pull-up resistor, default = logic
high
Table 1. EN Pin (20 MHz, 100 MHz and 300 MHz Clocks)
EN PIN
1
0
DESCRIPTION
All HCLK outputs, and 20-MHz outputs enabled, detailed device configurations are determined by 2-wire serial interface
settings.
All HCLK = true Hi-Z, both PLLs are powered down and 20-MHz output in Hi-Z and Crystal Oscillator disabled, EN overrides
2-wire serial interface settings.
2
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