TMS320VC33 Datasheet, PDF (48/57 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004
HOLD timing (continued)
H3
H1
HOLD
HOLDA
STRB, PAGEx
R/W
A[23:0]
tsu(HOLD−H1L)
tw(HOLD)
tv(H1L-HOLDA)
td(H1L-SH)H
tsu(HOLD−H1L)
tw(HOLDA)
tdis(H1L-S)
tdis(H1L-RW)
tdis(H1L-A)
tv(H1L−HOLDA)
ten(H1L-S)
ten(H1L-RW)
ten(H1L-A)
D[31:0]
Write Data
tdis(H1H-D)
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 33. Timing for HOLD/HOLDA (After Write)
H3
H1
HOLD
HOLDA
STRB, PAGEx
R/W
A[23:0]
tsu(HOLD−H1L)
tw(HOLD)
tv(H1L−HOLDA)
td(H1L-SH)H
tsu(HOLD−H1L)
tw(HOLDA)
tdis(H1L-S)
tdis(H1L-RW)
tdis(H1L-A)
tv(H1L−HOLDA)
ten(H1L-S)
ten(H1L-RW)
ten(H1L-A)
D[31:0]
Read Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 34. Timing for HOLD/HOLDA (After Read)
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