TMS320VC33 Datasheet, PDF (44/57 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal.
NOTE: The IACK instruction can be executed at anytime to signal an event using the IACK pin. The IACK
instruction is most often used within an interrupt routine to signal which interrupt has occurred. The IACK
instruction must be executed to generate the IACK pulse.
switching characteristics over recommended operating conditions for IACK (see Figure 30)
PARAMETER
td(H1H-IACKL) Delay time, H1 high to IACK low
td(H1H-IACKH) Delay time, H1 high to IACK high
VC33-120
MIN MAX
−1
4
−1
4
VC33-150
MIN MAX
−1
3
−1
3
UNIT
ns
ns
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
H3
H1
IACK
ADDR
td(H1H-IACKL)
td(H1H-IACKH)
Data
Figure 30. Interrupt Acknowledge (IACK) Timing
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