TMS320VC33 Datasheet, PDF (43/57 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

interrupt response timing (continued)
H3
TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H1
tsu(INT-H1L)^†
INT3 −INT0 Pin
(EDGEMODE = 0)
INT3 −INT0 Pin
(EDGEMODE = 1)
INT3 −INT0
Flag
tsu(INT-H1L)^‡
th(H1L-INT)
tsu(INT-H1L)^¶
tw(INT)^§
ADDR
Data
Vector Address
First Instruction Address
† _{Falling edge of H1 just detects INTx falling edge.}
‡ _{Falling edge of H1 detects second INTx low, however flag clear takes precedence.}
§ _{Nominal width}
¶ _{Falling edge of H1 misses previous INTx low as INTx rises.}
Figure 29. INT3−INT0 Response Timing
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