TMS320VC33 Datasheet, PDF (33/57 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

memory read/write timing (continued)
TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004
H3
H1
td(H1L-SL)
PAGEx, STRB
td(H1L-SH)
R/W
td(H1L-A)
tv(A-D)
td(H1H-RWL)W
A[23:0]
td(A-RDY)
D[31:0]
tsu(RDY-H1H)
tsu(D-H1L)R
th(H1L-D)R
th(H1H-RDY)
RDY
NOTE A: STRB remains low during back-to-back read operations.
Figure 20. Timing for Memory (STRB = 0 and PAGEx = 0) Read
H3
H1
PAGEx, STRB
td(H1L-SL)
td(H1L-SH)
R/W
A[23:0]
td(H1H-RWL)W
td(H1L-A)
td(H1H-A)W
td(H1H-RWH)W
D[31:0]
tv(H1L-D)W
RDY
tsu(RDY-H1H)
th(H1H-D)W
th(H1H-RDY)
Figure 21. Timing for Memory (STRB = 0 and PAGEx = 0) Write
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