TLC5970 Datasheet, PDF (42/48 Pages) Texas Instruments – 3-Channel, 12-Bit, PWM LED Driver with Buck DC/DC Converter and Differential Signal Interface

TLC5970
SBVS140 – MARCH 2010
www.ti.com
EEPROM Data Write Procedure
The DC data and the maximum on-duty data can be programmed into the EEPROM with the following
procedure:
1. Turn on the VCC power supply.
2. Set the VROM pin voltage to 19 V ± 0.5 V. The supply current is 5 mA (typical). The buck converter stops
while the VROM pin is held at the voltage.
3. Write the data for EEPROM write data latch 1 with the address. Write the command and the write data to
EEPROM data latch address.
4. Wait for more than 40 ms without data transfer. The maximum wait time is unlimited.
5. Stop supplying 19 V to the VROM pin and release the pin.
6. Write the grayscale data to turn on the LED and check LED brightness.
7. If the brightness must be adjusted, send new dot correction data to the DC data latch for brightness adjust.
8. Check the brightness again.
9. Repeat steps 8 and 9 to determine the best DC data.
10. Write the best DC data to the EEPROM write data latch 2 using steps 3 to 5 in this sequence.
Readout Register
EEPROM Data Readout Register (Register Address = 1011b)
When any data are written to this register address, the programed data in the EEPROM are loaded to the lower
36 bits in the 40-bit shift register from this readout register (register address = 1011b). The higher 4-bit data in
the 40-bit shift register are not changed from 1011b. The loaded data can be read out from SDTY and SDTZ and
syncronized by the shift clock generated from SCKA and SCKB. The data bit assignments are shown in Table 17
and Figure 34.
BIT NUMBER
6-0
13-7
20-14
23-21
28-24
30-29
34-31
35
Table 17. EEPROM Data Readout Register Bit Assignment
BIT NAME
RDDC0
RDDC1
RDDC2
RDONDTY
RDVFB
RDDSI
RDDLY
RDRSV
DESCRIPTION
Dot correction data for OUT0 in EEPROM (7-bit data)
Dot correction data for OUT1 in EEPROM (7-bit data)
Dot correction data for OUT2 in EEPROM (7-bit data)
On-duty (4-bit data)
FB target voltage (5-bit data)
DSI mode (2-bit data)
Internal data latch pulse delay time (4-bit data)
TI reserved data (1-bit data, no fixed data)
EEPROM Data Read Out Register
MSB
LSB
35
34-31 30-29 28-24 23-21
20
14
13
12-7
6
0
TI
Latch DSI Timing FB Target PH on
Reserved Delay Time Mode Voltage Duty
Bit 0 Bits[3:0] Bits[1:0] Bits[4:0] Bits[2:0]
OUT2
OUT2
¼ _{DC Data}
DC Data
Bit 6
Bit 0
OUT1
OUT1
¼ _{DC Data}
DC Data
Bit 6
Bit 0
OUT0
OUT0
¼ _{DC Data}
DC Data
Bit 6
Bit 0
Figure 34. EEPROM Data Readout Register Bit Assignment
42
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