TLC5970 Datasheet, PDF (29/48 Pages) Texas Instruments – 3-Channel, 12-Bit, PWM LED Driver with Buck DC/DC Converter and Differential Signal Interface

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TLC5970
SBVS140 – MARCH 2010
SDTA
SDTB
SCKA
SCKB
The latch pulse is generated after _{Pre-Boost Period}
the programmed time from the
Generated Shift Clock
last serial clock rising edge. ₁
2
17 18
(Internal)
1040 1041
4111 4112 1
2
Generated Shift Register Data
(Internal)
Generated Latch Pulse
(Internal)
The GS first and second latches are updated at the same time when the latch pulse
is generated with the display timing reset mode enabled.
GS First Latch Data
(Internal)
GS Second Latch Data
(Internal)
1/2 Divided Internal Oscillator Clock
(Internal)
Grayscale Counter
(Internal)
Function Control Bit 13
(External GS clock)
Function Control Bit 14
(Display Timing Reset)
OUTn
(GSDATA = 000h)
OUTn
(GSDATA = 001h)
OUTn
(GSDATA = 002h)
OUTn
(GSDATA = 3FFh)
OUTn
(GSDATA = 400h)
1
0
1
0
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
XXX FF0 FF1
001 002
400 401 FFE FFF 000 001 002
GS counter is set to FF0h when the latch pulse is generated for
GS data when the display timing reset bit is '1'.
No drivers turn on when
grayscale data are '0'.
T = Shift Clock ´ 1
OUTn is not turned on again until the next latch pulse is input for
auto repeat off mode (AutoRpt bit of the function control latch = 0).
OUTn is turned on again for auto repeat on mode
(AutoRpt bit of the function control latch = 1).
T = Shift Clock ´ 1023
T = Shift Clock ´ 1024
OUTn
(GSDATA = 401h)
OFF
ON
OUTn
(GSDATA = FFEh)
OUTn
(GSDATA = FFFh)
OFF
ON
T = Shift Clock ´ 4094
OFF
ON
T = Shift Clock ´ 4095
Figure 23. PWM Operation (External GS Clock Mode)
Copyright © 2010, Texas Instruments Incorporated
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