TLC5970 Datasheet, PDF (31/48 Pages) Texas Instruments – 3-Channel, 12-Bit, PWM LED Driver with Buck DC/DC Converter and Differential Signal Interface

TLC5970
www.ti.com
SBVS140 – MARCH 2010
REGISTER AND DATA LATCH CONFIGURATION
The TLC5970 has five writable data latches, two readable registers, and one error release address. All data
written into or read from these registers and data latches go through the differential signal interfaces and the
40-bit Common Shift Register. The first four most significant bits (MSBs) in the 40-bit Common Shift Register are
used to define which internal latch the data are transferred into. Data in the 40-bit Common Shift Register are
automatically transferred into an internal latch or data from the internal latch are automatically transferred into the
40-bit Common Shift Register when the TLC5970 generates the internal latch signal. Figure 25 shows the shift
register and data latch configurations. Table 7 lists the assignment of latch addresses.
BINARY
0000
0001-1000
1001
1010
1011
1100
1101
1110
1111
Table 7. Register/Data Latch Address Assignment
ADDRESS (4-Bit)
DECIMAL
0
1-8
HEX
0
1-8
9
9
10
A
11
B
12
C
13
D
14
E
15
F
READ/WRITE
W
—
W
R
R
W
W
W
W
SELCTED DATA LATCH/FUNCTION
Grayscale (GS) data latch. These data control LED
brightness by PWM.
No assigned latch. Data are not transferred when these
addresses are selected.
Restart operation.
If the TLC5970 is disabled because of overvoltage
protection (OVP) or short-circuit protection (SCP), writing
any value to the Restart Operation latch enables the
TLC5970. Writing to this latch has no effect if the TLC5970
is operating normally. The system should diagnose and
correct any problems that have caused OVP or SCP before
writing to this latch to restart the IC.
Status Information Data (SID) Register. Writing any value
to this register causes the SID data to be loaded into the
40-bit Common Shift Register.
EEPROM Data Read Register. Writing any value to this
register causes the EEPROM data to be loaded into the
40-bit Common Shift Register.
EEPROM1 Write Data Latch (write command = A5h).
The data in this latch program the PH on-duty, VFB target
voltage, differential interface timing mode. and Internal latch
pulse delay time. In order to properly program the
EEPROM with this data, bits 35-28 must contain A5h
(1010101b).
EEPROM Write Data Latch 2 (write commend = 5Ah).
The data in this latch program the default Dot Correction. In
order to properly program the EEPROM with this data, bits
35-28 must contain 5Ah (0101010b).
Dot Correction (DC) Data Latch.
The data in this latch contain OUTn DC data. When the IC
is powered up, the data stored in EEPROM2 are
automatically written to this latch.
Function Control (FC) and Brightness Control (BC) Data
Latch.
These data control several IC functions. This latch also
contains the Brightness Control data.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TLC5970
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