ADS5527_07 Datasheet, PDF (42/57 Pages) Texas Instruments – 12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5527
SLWS196A – DECEMBER 2006 – REVISED MAY 2007
www.ti.com
Figure 50. Eye Diagram of LVDS Data Output With Internal Termination
Parallel CMOS
In this mode, the 12 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data
bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the
rising edge of the output clock. The output clock is CLKOUT (pin 5).
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin (see Figure 36). The maximum DRVDD current occurs when each output bit toggles between 0 and 1
every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be
determined by the average number of output bits switching, which is a function of the sampling frequency and
the nature of the analog input signal.
Digital current due to CMOS output switching = C_L x V_DRVDD x (N x F_AVG)
where C_L = load capacitance, N x F_AVG = average number of output bits switching
Figure 36 shows the current with various load capacitances across sampling frequencies at 2MHz analog input
frequency.
Output Switching Noise and Data Position Programmability (in CMOS mode ONLY)
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant
of sampling and degrade the SNR. To minimize this, the device includes programmable options to move the
output data transitions with respect to the output clock. This can be used to position the data transitions at the
optimum place away from the sampling instant and improve the SNR. Figure 21 shows the variation of SNR for
different CMOS output data positions at 190 MSPS.
Note that the optimum output data position varies with the sampling frequency. The data position can be
programmed using the register bits <DATA POSN> (Table 9).
It is recommended to put series resistors (50 to 100 Ω) on each output line placed very close to the converter
pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of
switching noise. For example, the data in Figure 21 was taken with 50 Ω series resistors on each output line.
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