ADS5527_07 Datasheet, PDF (20/57 Pages) Texas Instruments – 12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5527
SLWS196A – DECEMBER 2006 – REVISED MAY 2007
Table 15. Serial Register G
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
<ODI> OUTPUT DATA
6C
INTERFACE - DDR LVDS OR
PARALLEL CMOS
D1
1
D4 - D3
00
01
11
<RST> Software resets the ADC
Resets all registers to default values
<ODI> Output data interface
DDR LVDS outputs, default after reset
DDR LVDS outputs
Parallel CMOS outputs
Table 16. Serial Register H
A7 - A0
D7
D6
D5
D4
D3
D2
6D
<SCALING> POWER SCALING
<REF> INTERNAL or
EXTERNAL REFERENCE
D4
0
1
D7 - D5
001
011
101
111
A7 - A0
7E
<REF> Reference
Internal reference
External reference mode, force voltage on Vcm to set reference.
<SCALING> Program power scaling at lower sampling
frequencies
Use for Fs > 150 MSPS, default after reset
Power Mode 1, use for 105 < Fs ≤ 150 MSPS
Power Mode 2, use for 50 < Fs ≤ 105
Power Mode 3, use for Fs ≤ 50 MSPS
Table 17. Serial Register I
D7
D6
D5
D4
D3
D2
<DATA TERM> INTERNAL TERMINATION –
DATA OUTPUTS
<CLKOUT TERM> INTERNAL
TERMINATION – OUTPUT CLOCK
D1 - D0
00
01
10
11
<LVDS CURR> LVDS buffer current programming
3.5 mA, default
2.5 mA
4.5 mA
1.75 mA
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D1
D0
<RST>
SOFTWARE
RESET
D1
D0
D1
D0
<LVDS CURR> LVDS
CURRENT
PROGRAMMABILITY
20
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