ADS5527_07 Datasheet, PDF (41/57 Pages) Texas Instruments – 12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS5527
SLWS196A – DECEMBER 2006 – REVISED MAY 2007
CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
Sample N
Sample N+1
Figure 49. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mV_PP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA using the register bits <LVDS CURR> (Table 17). In addition, there exists a
current double mode, where this current is doubled for the data and output clock buffers (register bits <CURR
DOUBLE>, Table 18).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistences available are – 325, 200, and 170 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistences. This results in eight effective terminations from open (no
termination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 50 shows the eye diagram of one of the LVDS data outputs with a 10-pF load capacitance (from
each pin to ground) and 100-Ω internal termination enabled. The termination can be programmed using register
bits <DATA TERM> and <CLKOUT TERM> (Table 17).
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