ADS5527_07 Datasheet, PDF (39/57 Pages) Texas Instruments – 12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5527
www.ti.com
SLWS196A – DECEMBER 2006 – REVISED MAY 2007
APPLICATION INFORMATION (continued)
Power Scaling Modes
ADS5527 has a power scaling mode in which the device can be operated at reduced power levels at lower
sampling frequencies with no difference in performance. (See Figure 27)⁽¹⁾ There are four power scaling modes
for different sampling clock frequency ranges, using the serial interface register bits <SCALING> (Table 16).
Only the AVDD power is scaled, leaving the DRVDD power unchanged.
Table 19. Power Scaling vs Sampling Speed
Sampling Frequency
MSPS
> 150
105 to 150
50 to 105
< 50
Power Scaling Mode
Default
Power Mode 1
Power Mode 2
Power Mode 3
Analog Power
(Typical)
1010 mW at 210 MSPS
841 mW at 150 MSPS
670 mW at 105 MSPS
525 mW at 50 MSPS
Analog Power in Default Mode
1010 mW at 210 MSPS
917 mW at 150 MSPS
830 mW at 105 MSPS
760 mW at 50 MSPS
(1) The performance in the power scaling modes is from characterization and not tested in production.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
Digital Output Information
ADS5527 provides 12-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided
to power down the output buffers and put the outputs in high-impedance state.
Output Interface
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS (see Table 6) or the serial interface register bit <ODI> (Table 15).
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