LM3S9B90 Datasheet, PDF (419/1185 Pages) Texas Instruments – Stellaris® LM3S9B90 Microcontroller

Stellaris® LM3S9B90 Microcontroller
Bit/Field
7:6
5:4
3:2
Name
WRWS
RDWS
reserved
Type
R/W
R/W
RO
Reset
0x0
0x0
0x0
Description
Write Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of WRn (or the falling
edge of WR). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0 No wait states.
0x1 1 wait state.
0x2 2 wait states.
0x3 3 wait states.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the same number of wait states is added to both
CS0n and CS1n accesses.
Read Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of RDn/Oen (or the falling
edge of RD). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0 No wait states.
0x1 1 wait state.
0x2 2 wait states.
0x3 3 wait states.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the same number of wait states is added to both
CS0n and CS1n accesses.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2010
419
Texas Instruments-Advance Information