ADS6424_10 Datasheet, PDF (40/71 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
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APPLICATION INFORMATION (continued)
1
0
−1
−2
−3
−4
−5
−6
0
100 200 300 400 500 600 700
f_IN − Input Frequency − MHz
G073
Figure 65. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 67 )
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has
to be taken into account. Figure 66 shows that the impedance (Zin, looking into the ADC input pins) decreases at
high input frequencies. The smith chart shows that the input impedance is capacitive and can be approximated
by a series R-C upto 500 MHz.
40 Copyright © 2007, Texas Instruments Incorporated
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