ADS6424_10 Datasheet, PDF (11/71 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

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ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
TIMING SPECIFICATIONS (continued)
Typical values are at 25°C, min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP clock amplitude, C_L = 5 pF , I_O = 3.5 mA,
R_L = 100 Ω , no internal termination, unless otherwise noted.
PARAMETER
TEST
CONDITIONS
ADS6424
F_s = 105 MSPS
MIN TYP MAX
ADS6423
F_s = 80 MSPS
MIN TYP MAX
ADS6422
F_s = 65 MSPS
MIN TYP MAX
UNIT
t_RISE
Bit clock and
Frame clock rise
time
From –100 mV to
+100 mV
50
100 200
50 100 200
50 100 200
ps
t_FALL
Bit clock and
Frame clock fall
time
From +100 mV to
–100 mV
50
100 200
50 100 200
50 100 200
ps
Bit clock duty
cycle
45% 50% 55% 45% 50% 55% 45% 50% 55%
Frame clock duty
cycle
47% 50% 53% 47% 50% 53% 47% 50% 53%
Input
Signal
Sample
N
Sample
N+11
t_A
Input
Clock
CLKM
CLKP
Bit ^DCLKP
Clock _DCLKM
Latency 12 Clocks
Sample
N+12
t_{PD_CLK}
Sample
N+13
Output
Data
DOP
DOM
Frame ^FCLKM
Clock _FCLKP
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sample N–1
Sample N
T0105-03
Figure 1. Latency
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