ADS6424_10 Datasheet, PDF (17/71 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

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ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD = LVDD =
3.3 V, unless otherwise noted.
f_SCLK
t_SLOADS
t_SLOADH
t_DSU
t_DH
PARAMETER
SCLK Frequency, f_SCLK = 1/t_SCLK
SEN to SCLK Setup time
SCLK to SEN Hold time
SDATA Setup time
SDATA Hold time
Time taken for register write to take effect after 16th SCLK falling edge
MIN
> DC
TYP MAX
20
25
25
25
25
100
UNIT
MHz
ns
ns
ns
ns
ns
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD = LVDD =
3.3 V, unless otherwise noted.
PARMATER
CONDITIONS
t₁ Power-on delay time
Delay from power-up of AVDD and LVDD to RESET pulse active
t₂ Reset pulse width
Pulse width of active RESET signal
t₃ Register write delay time Delay from RESET disable to SEN active
t_PO Power-up delay time
Delay from power-up of AVDD and LVDD to output stable
MIN TYP
5
10
25
6.5
MAX
UNIT
ms
ns
ns
ms
Power Supply
AVDD, LVDD
t₁
RESET
t₂
SEN
Figure 5. Reset Timing
t₃
T0108-03
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