ADS6424_10 Datasheet, PDF (1/71 Pages) Texas Instruments – QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE

ADS6424
ADS6423
ADS6422
www.ti.com _{............................................................................................................................................. SLAS532A – MAY 2007 – REVISED JUNE 2007}
QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE
FEATURES
1
• 12-Bit Resolution With No Missing Codes
• Simultaneous Sample and Hold
• 3.5dB Coarse Gain and upto 6dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
• Serialized LVDS Outputs With Programmable
Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
Clock Inputs and Amplitude down to 400
mV_PP
• Internal Reference With External Reference
Support
• No External Decoupling Required for
References
• 3.3-V Analog and Digital Supply
• 64 QFN Package (9 mm × 9 mm)
• Pin Compatible 14-Bit Family (ADS644X -
SLAS531A)
• Feature Compatible Dual Channel Family
(ADS624X - SLAS542A, ADS622X - SLAS543A)
APPLICATIONS
• Base-station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment
Table 1. ADS64XX Quad Channel Family
ADS644X
14 Bit
ADS642X
12 Bit
125 MSPS
ADS6445
ADS6425
(SLWS197)
105 MSPS
ADS6444
ADS6424
80 MSPS
ADS6443
ADS6423
65 MSPS
ADS6442
ADS6422
Table 2. Performance Summary
SFDR, dBc
Fin = 10MHz (0 dB gain)
Fin = 170MHz (3.5 dB gain)
Fin = 10MHz (0 dB gain)
SINAD, dBFS
Fin = 170MHz (3.5 dB gain)
Power per channel, mW
ADS6425
90
79
70.7
67.4
420
ADS6424
91
81
71.1
68.1
340
ADS6423
91
82
71.3
68.2
300
ADS6422
93
83
71.3
68.7
265
DESCRIPTION
The ADS6424/ADS6423/ADS6422 (ADS642X) is a family of high performance 12-bit 105/80/65 MSPS quad
channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact
64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB
coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to
the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS642X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical
applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data
sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated 1