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THS8133_07 Datasheet, PDF (4/25 Pages) Texas Instruments – TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION
THS8133, THS8133A, THS8133B
TRIPLE 10ĆBIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRIĆLEVEL SYNC GENERATION
SLVS204C − APRIL 1999 − REVISED SEPTEMBER 2000
(continued)
device configuration
Input data to the device can be supplied from a 3x10b GBR/YPbPr input port. If the device is configured to take
data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at the
full clock speed of CLK.
device configuration (continued)
In the case of 4:2:2 sampled data (for YPbPr) the device can be fed over either a 2x10 bit or 1x10 bit multiplexed
input port. An internal demultiplexer will route input samples to the appropriate DAC: Y at the rate of CLK, Pb
and Pr each at rate of one-half CLK.
According to ITU-BT.656 the sample sequence is Pb-Y-Pr over a 1x10 bit interface (Y-port). The sample
sequence starts at the first rising edge of CLK after BLANK has been taken high (inactive). In this case the
frequency of CLK is two times the Y conversion speed and four times the conversion speed of both Pr and Pb.
With a 2x10 bit input interface, both the Y-port and the Pr-port are sampled on every CLK rising edge. The Pr-port
carries the sample sequence Pb-Pr. The sample sequence starts at the first rising edge of CLK after BLANK
has been taken high (inactive). In this case the frequency of CLK is equal to the conversion speed of Y and 2x
the conversion speed of both Pr and Pb.
The device’s operation mode is set by the M1 and M2 mode selection terminals, according to Table 1. The
operation mode also determines the blanking level, as explained below in the sync/blanking generation
sections.
Table 1. THS8133 Configuration
M1 M2_INT CONFIGURATION
DESCRIPTION
L
L
GBR
3x10b−4:4:4
GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R input channels. For the
definition of the analog output levels during blanking, see note 1.
L
H
YPbPr
3x10b−4:4:4
YPbPr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Pb and Pr input channels. (see
Note 1). For the definition of the analog output levels during blanking, see note 1.
H
L
YPbPr
2x10b−4:2:2
YPbPr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK from Y & Pr input channels. A
sample sequence of Pb−Pr−... should be applied to the Pr port. At the first rising edge of CLK after
BLANK is taken high, Pb should be present on this port. For the definition of the analog output levels
during blanking, see note 1.
H
H
YPbPr
1x10b−4:2:2
YPbPr mode 4:2:2 1x10 bit (ITU-BT.656 compliant). Data clocked in on each rising edge of CLK from
Y input channel. For the definition of the analog output levels during blanking, see note 1.
NOTE 1: In all device versions, the blanking level on the AGY channel output corresponds to input code 0 of the DAC.
S
In the THS8133CPHP and the THS8133ACPHP versions, the blanking level on the ABPb and ARPr channel outputs corresponds to
the 512 input code of the DAC, when sync is inserted on all three channels (INS3_INT=H) and to the 0 input code of the DAC, when
sync is only inserted on the Y channel (INS3_INT=L)
S
In the THS8133BCPHP version, the blanking level on the ABPb and ARPr channel outputs corresponds to the 512 input code of the
DAC irrespective if sync is inserted on all three channels (INS3_INT=H), or if sync is inserted only on the Y channel (INS3_INT=L)
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