THS8133_07 Datasheet, PDF (10/25 Pages) Texas Instruments – TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION

THS8133, THS8133A, THS8133B
TRIPLE 10ĆBIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRIĆLEVEL SYNC GENERATION
SLVS204C − APRIL 1999 − REVISED SEPTEMBER 2000
recommended operating conditions over operating free-air temperature range, T_A (continued)
digital and reference inputs
MIN NOM MAX UNIT
High-level input voltage, VIH
DVDD = 3.3 V
DVDD = 5 V
2
DVDD
V
2.4
DVDD
Low−level input voltage, VIL
DVSS
0.8 V
Clock frequency, fclk
0
80 MHz
Pulse duration, clock high, tw(CLKH)
5
ns
Pulse duration, clock low, tw(CLKL)
Reference input voltage,† Vref(I) (see Note 3)
5
ns
1.35 1.62 V
FSADJ resistor, R(FS) (see Note 3)
360 430
Ω
† _{Voltage reference input applies to the externally applied voltage (overdrive condition). Internally a 2 kΩ resistor isolates the internal reference}
from the externally applied voltage, if any.
NOTE 3: The combination of Vref and RFS can be chosen at will as long as the maximum full-scale DAC output current I(FS) does not exceed 120%
of its nominal value. Therefore, at fixed R(FS) = R(FSnom), Vref should not be higher than the maximum value mentioned and at fixed
Vref = Vref(nom), R(FS) should not be less than the minimum value mentioned.
electrical characteristics over recommended operating conditions with f_CLK = 80 MSPS and use
of internal reference voltage V_ref, with R_(FS) = R_(FSnom) (unless otherwise noted)
power supply (1 MHz, −1 dBFS digital sine simultaneously applied to all 3 channels)
PARAMETER
IDD Operating supply current
PD Power dissipation
TEST CONDITIONS
AVDD = DVDD = 5 V
AVDD = 5 V, DVDD = 3.3
AVDD = DVDD = 5 V
AVDD = 5 V, DVDD = 3.3
MIN TYP MAX UNIT
134 142
mA
114 121
670 710
mW
525 565
digital inputs − dc characteristics
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
IIH
IIL
IIL(CLK)
IIH(CLK)
High-level input current
Low-level input current
Low-level input current, CLK
High-level input current, CLK
AVDD = DVDD = 5 V
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 5 V for IIH
−1
1 µA
−1 µA
1 µA
CI
Input capacitance
TA = 25_C
7
pF
ts
Data and control inputs setup time
3
ns
tH
Data and control inputs hold time
0
ns
td(D)
Digital process delay from first registered color
component of pixel‡ (see Figures 3−5)
RGB and YPbPr 4:4:4
YPbPr 4:2:2 2×10 bit
YPbPr 4:2:2 1×10 bit
7
8
CLK
periods
9
‡ _{This parameter is assured by design and not production tested. The digital process delay is defined as the number of CLK cycles required for}
the first registered color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and
appear at the DAC output drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers.
10
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