THS8133_07 Datasheet, PDF (2/25 Pages) Texas Instruments – TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION WITH TRI-LEVEL SYNC GENERATION

THS8133, THS8133A, THS8133B
TRIPLE 10ĆBIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRIĆLEVEL SYNC GENERATION
SLVS204C − APRIL 1999 − REVISED SEPTEMBER 2000
AVAILABLE OPTIONS
PACKAGE
TA
TQFP-48 PowerPAD
THS8133CPHP†
0°C to 70°C
THS8133ACPHP‡
THS8133BCPHP‡
† _{In the THS8133CPHP, the KIMBAL maximum specification is}
assured over full temperature range and the KIMBAL(SYNC)
maximum specification is assured at 25°C. The position of
the blanking level is as shown in Table 1.
‡ _{In the THS8133ACPHP and the THS8133BCPHP, both the}
KIMBAL maximum speciffication and the KIMBAL(SYNC)
maximum specification are assured over the full temperature
range. The position of the blanking level is as shown in Table
1.
Terminal Functions
TERMINAL
NAME
I/O
PIN
DESCRIPTION
ABPb
AGY
45 O Analog red, green and blue respectively Pr, Y and Pb current outputs, capable of directly driving a doubly
41
O ^{terminated 75-Ω coaxial cable.}
ARPr
43 O
AVDD
AVSS
BLANK
40,44
42,46
23
I Analog power supply (5 V ±10%). All AVDD terminals must be connected.
I Analog ground
I Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY and
ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes
precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) will result in sync generation.
BPb0−BPb9 10−1
I Blue or Pb pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
different operating modes.
CLK
26
I Clock input. A rising edge on CLK latches RPr0-9, GY0-9, BPb0-9, BLANK, SYNC, and SYNC_T. The M2 input is
latched by a rising edge on CLK also, but only when additional conditions are satisfied, as explained in its
terminal description.
COMP
DVDD
DVSS
FSADJ
39
O Compensation terminal. A 0.1 µF capacitor must be connected between COMP and AVDD.
12
I Digital power supply (3-V to 5-V range)
11
I Digital ground
38
I Full-scale adjust control. The full-scale current drive on each of the output channels is determined by the value of
a resistor RFS connected between this terminal and AVSS. The nominal value of RFS is 430 Ω, corresponding to
26.67 mA full-scale current. The relationship between RFS and the full-scale current level for each operation
mode is explained in the functional description.
GY0−GY9
36−27 I Green or Y pixel data input bus. Index 0 denotes the least significant bit. Refer to functional description for
different operating modes.
M1
47
I Operation mode control 1. M1 is directly interpreted by the device (it is not latched by CLK). M1 configures device
according to Table 1.
M2
48
I Operation mode control 2. The second rising edge on CLK after a transition on SYNC latches M2. The
interpretation is dependent on the polarity of the last SYNC transition:
SYNC L to H: latched as M2_INT
SYNC H to L: latched as INS3_INT
Together with M1, M2_INT configures the device as shown in Table 1. When INS3_INT is high, the sync output is
inserted on all DAC outputs; a low will insert it only on the AGY output. See also Figure 2 and Table 2. The value of
M2 at power up is undetermined. Therefore at least 1 L −>H transition on SYNC is required to set M2.
2
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443