THS10082 Datasheet, PDF (4/37 Pages) Texas Instruments – 10 bit TWO ANALOG INPUT, 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER

THS10082
SLAS254B – MAY 2002 – REVISED NOVEMBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 8 MHz, fI = 2 MHz at –1 dB (unless otherwise noted)
AC SPECIFICATIONS, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SINAD Signal-to-noise ratio + distortion
Differential mode
56
59
dB
Single-ended mode(1)
55
58
dB
SNR Signal-to-noise ratio
Differential mode
59
61
dB
Single-ended mode(1)
60
dB
THD Total harmonic distortion
Differential mode
Single-ended mode
–67 –61 dB
–63
dB
ENOB Effective number of bits
Differential mode
9 9.5
Bits
Single-ended mode(1)
9.35
Bits
SFDR Spurious free dynamic range
Differential mode
Single-ended mode
61
65
dB
64
dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full-scale sinewave, –3 dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full-scale sinewave, –3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100-mVpp sinewave, –3 dB
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100-mVpp sinewave, –3 dB
54
MHz
(1) _{The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling}
clock.
TIMING REQUIREMENTS⁽¹⁾
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
td(DATA_AV)
td(o)
Delay time
Delay time
tpipe
Latency
(1) _{See Figure 27.}
TEST CONDITIONS
MIN TYP MAX UNIT
5
ns
5
ns
5
CONV
CLK
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE⁽¹⁾
tc
tw1
td(A)
t2
PARAMETER
Clock cycle of the internal clock oscillator
Pulse duration, CONVST
Aperture time
Delay time between consecutive start of
single conversion
Delay time, DATA_AV becomes active for the
td(DATA_AV) _{trigger level condition: TRIG0 = 1, TRIG1 = 1}
(1) _{See Figure 26.}
TEST CONDITIONS
One analog input
Two analog inputs
One analog input
Two analog inputs
One analog input, TL = 1
Two analog inputs, TL = 2
One analog input, TL = 4
Two analog inputs, TL = 4
One analog input, TL = 8
Two analog inputs, TL = 8
One analog input, TL = 14
Two analog inputs, TL = 12
MIN
117
1.5×tc
2.5×tc
2×tc
3×tc
TYP
125
MAX UNIT
133 ns
ns
1
ns
ns
6.5×tc+15
ns
7.5×tc+15
3×t2 +6.5×tc+15
ns
t2 +7.5×tc+15
7×t2 +6.5×tc+15
ns
3×t2 +7.5×tc+15
13×t2 +6.5×tc+15
ns
13×t2 +6.5×tc+15
4