THS10082 Datasheet, PDF (30/37 Pages) Texas Instruments – 10 bit TWO ANALOG INPUT, 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER

THS10082
SLAS254B – MAY 2002 – REVISED NOVEMBER 2002
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Read Timing Parameter (RD-Controlled)
PARAMETER
tsu(CS)
ta
td(CSDAV)
th
th(CS)
tw(RD)
Setup time, RD low to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, RD change to first CS invalid
Pulse duration, RD active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
Write Timing (using WR, WR-Controlled)
Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input
RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal
of CS0, CS1, and WR which becomes valid.
CS0
CS1
tsu(CS)
tw(WR)
th(CS)
WR
10%
10%
RD^{ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ}
tsu ÔÔÔÔÔÔÔÔÔÔÔÔ
th
D(0–9)
90%
90%
DATA_AV ^{ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ}
Figure 39. Write Timing Diagram Using WR (WR-controlled)
Write Timing Parameter Using WR (WR-Controlled)
PARAMETER
tsu(CS)
tsu
th
th(CS)
tw(WR)
Setup time, CS stable to last WR valid
Setup time, data valid to first WR invalid
Hold time, WR invalid to data invalid
Hold time, WR invalid to CS change
Pulse duration, WR active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
30