THS10082 Datasheet, PDF (32/37 Pages) Texas Instruments – 10 bit TWO ANALOG INPUT, 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER

THS10082
SLAS254B – MAY 2002 – REVISED NOVEMBER 2002
AINP
AINM
VREFP
+
Σ ^VADC
–
10-Bit
ADC
VREFM
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Figure 41. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage (V_ADC) which is applied at the input of the
ADC is the difference between the input AINP and AINM. This means that V_REFM defines the minimum voltage (AINM)
which can be applied to the ADC. V_REFP defines the maximum voltage (AINP) which can be applied to the ADC. The voltage
V_ADC can be calculated as follows:
VADC + ABS(AINP–AINM)
(2)
An advantage to single-ended operation is that the common-mode voltage
VCM
+
AINM
)
2
AINP
(3)
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND v AINM, AINP v AVDD
(4)
1 V v VCM v 4 V
(5)
In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection which is common
to both analog inputs. See Figure 43.
SINGLE-ENDED MODE OF OPERATION
The THS10082 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the
THS10082 must be driven from an operational amplifier that does not degrade the ADC performance. Because the
THS10082 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its
input requirements. This can be achieved with dc and ac coupling. An application example is shown for dc-coupled level
shifting in the following section, dc coupling.
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