THS10082 Datasheet, PDF (29/37 Pages) Texas Instruments – 10 bit TWO ANALOG INPUT, 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER

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THS10082
SLAS254B – MAY 2002 – REVISED NOVEMBER 2002
INTERFACING THE THS10082 TO THE TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS10082 to the TMS320C30/31/33 DSPs. The read and write
timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
DVDD
THS10082
CS0
CS1
RD R/W
DATA_AV
CONV_CLK
DATA
TMS320C30/31/33
STRB
A23
R/W
INTX
TOUT
DATA
INTERFACING THE THS10082 TO THE TMS320C54X USING I/O STROBE
The following application circuit shows an interface of the THS10082 to the TMS320C54x. The read and write timings (using
R/W, CS0-controlled) shown before are valid for this specific interface.
DVDD
THS10082
CS0
CS1
RD R/W
DATA_AV
CONV_CLK
DATA
TMS320C54x
I/O STRB
A15
R/W
INTX
BCLK
DATA
Read Timing (Using RD, RD-Controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts
as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0,
CS1, and RD which becomes valid.
CS0
CS1
WR ^{ÓÓÓÓÓÓÓÓ}
RD
D(0–9)
DATA_AV
tsu(CS)
10%
tw(RD)
ta
90%
td(CSDAV)
90%
ÔÔÔÔÔÔ ^th(CS)
10%
th
90%
Figure 38. Read Timing Diagram Using RD (RD-controlled)
TMS320C30 is a trademark of Texas Instruments.
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