SN74ALVC7805 Datasheet, PDF (4/14 Pages) Texas Instruments – 256 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
Terminal Functions
TERMINAL
I/O
NAME
NO.
AF/AE
24
O
D0–D17
2–9, 11–12,
14–21
I
HF
22
O
IR
28
O
OE1
OE2
56
30
I
OR
29
O
PEN
23
I
33–34, 36–38,
Q0–Q17 40–43, 45–49, O
51, 53–55
RDCLK
32
I
RDEN
31
I
RESET
1
I
WRTCLK
25
I
WRTEN1
27
WRTEN2
26
I
DESCRIPTION
Almost-full/almost-empty flag. Depth-offset values can be programmed for this flag, or the default
value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is
high when memory contains X or fewer words or (256 – Y) or more words. AF/AE is high after reset.
18-bit data input port
Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset.
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO
is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition
of WRTCLK after reset.
Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on
a low-to-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and the data
outputs are in the high-impedance state.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the
FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low
during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded
to empty memory.
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
18-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q17
on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When
OR is low, the last word read from the FIFO is present on Q0–Q17.
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A
low-to-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low and OR
is high. OR is synchronous to the low-to-high transition of RDCLK.
Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the
low-to-high transition of RDCLK.
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of
WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A
low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is high, and
IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on
a low-to-high transition of WRTCLK.
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