SN74ALVC7805 Datasheet, PDF (1/14 Pages) Texas Instruments – 256 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
D Member of the Texas Instruments
Widebus™ Family
D Low-Power Advanced CMOS Technology
D Operates From 3-V to 3.6-V V_CC
D Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D Read and Write Operations Synchronized
to Independent System Clocks
D Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
D Bidirectional Configuration and Width
Expansion Without Additional Logic
D Input-Ready Flag Synchronized to Write
Clock
D Output-Ready Flag Synchronized to Read
Clock
D Fast Access Times of 13 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
D Data Rates up to 50 MHz
D Pin-to-Pin Compatible With SN74ACT7803,
SN74ACT7805, and SN74ACT7813
D Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Lead Spacing
description
The SN74ALVC7805 is suited for buffering
asynchronous data paths up to 50-MHz clock
rates and 13-ns access times. This device is
designed for 3-V to 3.6-V V_CC operation. Two
devices can be configured for bidirectional data
buffering without additional logic.
DL PACKAGE
(TOP VIEW)
RESET 1
D17 2
D16 3
D15 4
D14 5
D13 6
D12 7
D11 8
D10 9
V_CC 10
D9 11
D8 12
GND 13
D7 14
D6 15
D5 16
D4 17
D3 18
D2 19
D1 20
D0 21
HF 22
PEN 23
AF/AE 24
WRTCLK 25
WRTEN2 26
WRTEN1 27
IR 28
56 OE1
55 Q17
54 Q16
53 Q15
52 GND
51 Q14
50 V_CC
49 Q13
48 Q12
47 Q11
46 Q10
45 Q9
44 GND
43 Q8
42 Q7
41 Q6
40 Q5
39 V_CC
38 Q4
37 Q3
36 Q2
35 GND
34 Q1
33 Q0
32 RDCLK
31 RDEN
30 OE2
29 OR
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at
least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO
initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO
must be reset upon power up.
The SN74ALVC7805 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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