SN74ALVC7805 Datasheet, PDF (10/14 Pages) Texas Instruments – 256 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
timing requirements over recommended operating conditions (see Figures 1 through 5)
fclock Clock frequency
D0–D17 high or low
WRTCLK high or low
RDCLK high or low
tw
Pulse duration
PEN low
WRTEN1 high, WRTEN2 low
OE1, OE2 low
RDEN low
tsu
Setup time
D0–D17 before WRTCLK↑
WRTEN1, WRTEN2 before WRTCLK↑
OE1, OE2 before RDCLK↑
RDEN before RDCLK↑
Reset: RESET low before first WRTCLK↑
and RDCLK↑^†
th
Hold time
PEN before WRTCLK↑
D0–D17 after WRTCLK↑
WRTEN1, WRTEN2 after WRTCLK↑
OE1, OE2, RDEN after RDCLK↑
Reset: RESET low after fourth WRTCLK↑
and RDCLK↑^†
PEN low after WRTCLK↑
† _{To permit the clock pulse to be utilized for reset purposes}
’ALVC7805-20 ’ALVC7805-25 ’ALVC7805-40
MIN MAX MIN MAX MIN MAX
50
40
25
9
10
14
7
8
12
7
8
12
9
9
12
8
8
12
9
9
12
8
8
12
5
5
5
5
5
5
5
6
6
5
5
7
6
6
6
6
6
6
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
UNIT
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 50 pF (unless otherwise noted) (see Figure 5)
PARAMETER
FROM
(OUTPUT)
TO
(INPUT)
’ALVC7805-20 ’ALVC7805-25 ’ALVC7805-40
UNIT
MIN MAX MIN MAX MIN MAX
fmax
WRTCLK or RDCLK
50
40
25
MHz
RDCLK↑
Any Q
4
13
4
15
4
20
WRTCLK↑
IR
3
11
3
13
3
15
tpd
RDCLK↑
OR
3
11
3
13
3
15 ^ns
WRTCLK↑
RDCLK↑
AF/AE
7
19
7
19
7
21
7
21
7
23
7
23
tPLH
tPHL
tPLH
WRTCLK↑
RDCLK↑
RESET low
HF
HF
AF/AE
7
17
7
18
2
11
7
19
7
20
2
13
7
21 ns
7
22 ns
2
15 ns
tPHL
RESET low
HF
2
12
2
14
2
16 ns
ten
OE1, OE2
Any Q
2
11
2
11
2
14 ns
tdis
OE1, OE2
Any Q
2
11
2
14
2
14 ns
10
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