DRV103UG4 Datasheet, PDF (4/24 Pages) Burr-Brown (TI) – PWM LOW-SIDE DRIVER (1.5A and 3A) for Solenoids, Coils, Valves, Heaters, and Lamps

PIN CONFIGURATION
Top View
SO
Duty Cycle Adj 1
Delay Adj 2
Osc Freq Adj 3
GND 4
8 Input
7 Status OK Flag
6 +V_S
5 OUT
PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Duty Cycle Adjust
Internally, this pin connects to the input of a comparator and a (2.75 x I_REF) current source from V_S. The voltage at this node linearly
sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The
active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, output duty cycle is near
90%. At 1.5V, output duty cycle is near 10%.
Delay Adjust
This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than
1µs by tying the pin to 5V. This pin connects internally to a 3µA current source from V_S and to a 2.6V threshold comparator. When
the pin voltage is below 2.6V, the output device is 100% ON. The PWM oscillator is not synchronized to the Input (pin 1), so the
duration of the first pulse may be any portion of the programmed duty cycle.
Oscillator
Frequency Adjust
PWM frequency is adjustable. A resistor to ground sets the current I_REF and the internal PWM oscillator frequency. A range of 500Hz
to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors
higher than 10M will be required. The pin then becomes a very high impedance node and is, therefore, sensitive to noise pickup
and PCB leakage currents.
GND
This pin must be connected to system ground for the DRV103 to function. It carries the 0.4mA quiescent current plus the full load
current when the power DMOS transistor is switched on.
OUT
The output is the drain of a power DMOS transistor with its source connected to ground. Its low on-resistance (0.5Ω typ) assures
low power dissipation in the DRV103. Gate drive to the power device is controlled to provide a slew-rate limited rise and fall time.
This reduces radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off
cycle. The external diode should be selected for low forward voltage and low storage time. The internal clamp diode (an ESD
protection diode) provides some degree of back-EMF protection but it should not be used as a flyback diode.
+V_S
Status OK Flag
This is the power supply pin. Operating range is +8V to +32V. +V_S must be ≥ the supply voltage to the load.
Normally HIGH (active LOW), a Flag LOW signals either an over-temperature or over-current fault. The over-current flag (Status
OK) is LOW only when the output is ON (constant DC output or the “ON” portion of PWM mode). A thermal fault (thermal shutdown)
occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull-
up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA typical.
Input
The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the
typical switching threshold, 1.7V. Below this level, the output is disabled. Input current is typically 10nA when driven HIGH and 10nA
with the input LOW. The input should not be directly connected to the power supply (V_S) or damage will occur.
LOGIC BLOCK DIAGRAM
Status OK
Flag
+V_S
Input
On
Off
DRV103
Thermal Shutdown
Over Current
1.3V V_REF Oscillator
PWM
DMOS
ESD
Flyback
Diode
OUT
Load
DMOS
Delay
I_REF
Delay
Adj
C_D
Osc Freq
Adj
R_FREQ
2.75 • I_REF
Duty Cycle
Adj
R_PWM
GND
4
DRV103
SBVS029A