DRV103UG4 Datasheet, PDF (3/24 Pages) Burr-Brown (TI) – PWM LOW-SIDE DRIVER (1.5A and 3A) for Solenoids, Coils, Valves, Heaters, and Lamps

ELECTRICAL CHARACTERISTICS
At T_C = +25°C, V_S = +24V, Load = 100Ω, and 4.99kΩ “OK Flag” pullup to +5V, Delay Adj Capacitor = 100pF to Ground, Freq Adj Resistor = 205kΩ to Ground,
Duty Cycle Adj Resistor = 137kΩ to Ground, unless otherwise noted.
DRV103U, H
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT
Output Current⁽¹⁾
Output Saturation Voltage, Source
Current Limit^{(2), (10)}
Leakage Current
DIGITAL CONTROL INPUT⁽³⁾
V_CTR Low (output disabled)
V_CTR High (output enabled)
I_CTR Low (output disabled)
I_CTR High (output enabled)
Propagation Delay
DELAY TO PWM⁽⁴⁾
Delay Equation⁽⁵⁾
Delay Time
Minimum Delay Time⁽⁷⁾
DUTY CYCLE ADJUST
Duty Cycle Range
Duty Cycle Accuracy
vs Supply Voltage
Nonlinearity⁽⁸⁾
DYNAMIC RESPONSE
Output Voltage Rise Time
Output Voltage Fall Time
Oscillator Frequency Range
Oscillator Frequency
OK FLAG
Normal Operation
Fault⁽⁹⁰⁾
Sink Current
Over-Current Flag: Set
THERMAL SHUTDOWN
Junction Temperature
Shutdown
Reset from Shutdown
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance, θ_JA
SO-8 (U)
PowerPAD™ SO-8 (H)⁽¹⁰⁾
SO-8 Package (U)
PowerPAD™ SO-8 Package (H)
I_O = 1A
I_O = 0.1A
DMOS Output Off, V_O = +32V
V_CTR = 0V
V_CTR = +5.5V
On-to-Off and Off-to-On
DC to PWM Mode
C_D = 0.1µF
C_D = 0
50% Duty Cycle, 25kHz
50% Duty Cycle, V_S = V_O = +8V to +32V
10% to 90% Duty Cycle
V_O = 10% to 90% of V_S
V_O = 90% to 10% of V_S
External Adjust
R_OSC = 205kΩ
20kΩ Pull-Up to +5V
Sinking 1mA
V_OKFLAG = 0.4V
I_O = 0
1in² 0.5oz. Copper on PCB
1in² 0.5oz. Copper on PCB
1.5
3
+0.4
+0.6
+0.05
+0.07
3
3.5
4.2
±1
±10
0
+1.2
+2.2
+5.5
0.01
1
120
150
1
See Note (6)
90
110
140
18
10 to 90
±2
±2
1
0.2
2
0.2
2
0.5 to 100
20
25
30
+4.5
5.0
+0.22
+0.4
2
5
+160
+140
+24
+8
+32
0.4
0.8
–40
+85
–55
+125
–65
+150
150
68
A
A
V
V
A
µA
V
V
µA
µA
µs
s
ms
µs
%
%
%
% FSR
µs
µs
kHz
kHz
V
V
mA
µs
°C
°C
V
V
mA
°C
°C
°C
°C/W
°C/W
NOTES: (1) Output current is limited by internal current limit and by DRV103 power dissipation. (2) Output current resets to zero when current limit is reached.
(3) Logic High enables output (normal operation). (4) Constant DC output to PWM (Pulse-Width Modulated) time. (5) Maximum delay is determined by an external
capacitor. Pulling the Delay Adjust Pin LOW corresponds to an infinite (continuous) delay. (6) Delay to PWM ≈ C_D • 10⁶ (C_D in
F • 1.1). (7) Connecting the Delay Adjust Pin to +5V reduces delay time to less than 1µs. (8) V_IN at pin 3 to percent of duty cycle at pin 6. (9) OK Flag LOW indicates
fault from over-temperature or over-current conditions. (10) PowerPAD™ SO-8 (H) package has highest continuous current (2A) because the chip operates at a
lower junction temperature when underside metal tab is connected to a heat sink or heat spreader. θ_JA = 68°C/W measured on DRV103 demo board;
θ_JA = 58°C/W measured on JEDEC standard test board. H package θ_JC = 16.7°C/W.
DRV103
3
SBVS029A