BQ24030_07 Datasheet, PDF (4/38 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINY)

bq24030, bq24031, bq24032A
bq24035, bq24038
SLUS618F – AUGUST 2004 – REVISED NOVEMBER 2006
www.ti.com
ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ T_J ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT BIAS CURRENTS
I_CC(SPLY)
I_CC(SLP)
Active supply current, VCC
Sleep current (current into BAT
pin)
V_VCC > V_VCC(min)
V_(AC) < V_(BAT), V_(USB) < V_(BAT),
2.6 V ≤ V_I(BAT)≤ V_O(BAT-REG),
Excludes load on OUT pin
1
2 mA
2
5
I_CC(AS-STDBY)
I_{CC(USB-STDBY)}
I_{CC(BAT-STDBY)}
I_IB(BAT)
AC standby current
USB standby current
BAT standby current
Charge done current, BAT
V_I(AC) ≤ 6 V, Total current into AC pin
with chip disabled, Excludes all loads,
CE=LOW, after t_(CE-HOLDOFF) delay
Total current into USB pin with chip
disabled, Excludes all loads, CE=LOW,
after t_(CE-HOLDOFF) delay
Total current into BAT pin with AC
and/or USB present and chip disabled;
Excludes all loads (OUT and LDO),
CE=LOW, after t_(CE-HOLDOFF) delay,
0°C ≤ T_J≤ 85°C⁽¹⁾
Charge DONE, AC or USB supplying the
load
200
200
µA
45
60
1
5
HIGH AC CUTOFF MODE
V_CUT-OFF
V_I(AC) > 6.8 V, AC FET (Q1) turns off,
Input ac cutoff voltage, bq24035
USB FET (Q3) turns on if USB power
present, otherwise BAT FET (Q2) turns
6.1
6.4
6.8
V
on.
LDO OUTPUT
V_O(LDO)
Output regulation voltage
Regulation accuracy⁽²⁾
Active only if AC or USB is present,
V_I(OUT)≥ V_O(LDO) + (I_O(LDO) × R_DS(on))
–5%
3.3
V
5%
I_O(LDO)
Output current
R_DS(on)
On resistance
C_(OUT) ⁽³⁾
Output capacitance
OUT PIN-VOLTAGE REGULATION
OUT to LDO
20 mA
50
Ω
1
µF
V_O(OUT-REG)
Output
regulation
voltage
bq24030/31
bq24032A
bq24038
OUT PIN – DPPM REGULATION
V_I(AC)≥ 6 V+V_DO
V_I(AC)≥ 4.4 V+V_DO
VBSEL = HIGH or VBSEL = LOW,
V_I(AC) > 4.4 V+V_DO
6.0
6.3
4.4
4.5
V
4.4
4.5
V_(DPPM-SET)
I_(DPPM-SET)
SF
DPPM set point⁽⁴⁾
DPPM current source
DPPM scale factor
V_DPPM-SET < V_OUT
AC or USB present
V_(DPPM-REG)= V_(DPPM-SET) × SF
2.6
95
1.139
100
1.150
5
V
105
µA
1.162
(1) This includes the quiescent current for the integrated LDO.
(2) In standby mode (CE low) the accuracy is ±10%.
(3) LDO output capacitor not required but one with a value of 0.1 µF is recommended.
(4) V_(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V_(DPPM-REG).
4
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