BQ24030_07 Datasheet, PDF (15/38 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINY)

bq24030, bq24031, bq24032A
bq24035, bq24038
www.ti.com
SLUS618F – AUGUST 2004 – REVISED NOVEMBER 2006
V_{(DPPM−REG)} + I_(DPPM) R_(DPPM) SF
(1)
where
R_(DPPM) is the external resistor connected between the DPPM and VSS pins.
I_(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly
proportional to the programmed charging current. When the programmed charging current is reduced, due to
DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the
safety time. In normal operation, V(TMR) = 2.5 V; when the clock is slowed the voltage V(TMR) is reduced. For
example, if V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value. See
Figure 5 through Figure 8.
Case 2: USB (PSEL = Low) bq24030/31/32A/38
System Power
In this case, the system load is powered directly from the USB port through the internal switch Q3 (see
Figure 14). Note in this case, Q3 regulates the total current to the 100 mA or 500 mA level, as selected on the
ISET2 input. Switch Q1 is turned off in this mode. If the system and battery load is less than the selected
regulated limit, then Q3 is fully on and V_OUT is approximately (V_(USB)-V_(USB-DO)). The systems power management
is responsible for keeping its system load below the USB current level selected (if the battery is critically low or
missing). Otherwise, the output drops to the battery voltage; therefore, the system should have a low power
mode for USB power application. The DPPM feature keeps the output from dropping below its programmed
threshold, due to the battery charging current, by reducing the charging current.
Charge Control
When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin
(0.1/0.5 A). The charge current to the battery is set by the ISET1 resistor (typically > 0.5 A). Because the charge
current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage
or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until
V_OUT stops dropping. If V_OUT drops to the battery voltage, the battery is able to supplement the input current to
the system.
Dynamic Power-Path Management (DPPM)
The theory of operation is the same as described in CASE 1, except that Q3 restricts the amount of input current
delivered to the output and battery instead of the input supply.
Note that the DPPM voltage, V_(DPPM), is programmed as follows:
V_{(DPPM−REG)} + I_(DPPM) R_(DPPM) SF
(2)
and
V_{(DPPM−REG)} + V_{(DPPM−SET)} SF
(3)
where
R_(DPPM) is the external resistor connected between the DPPM and VSS pins.
I_(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
Feature Plots
The voltage on the DPPM pin, V_(DPPM-SET) is determined by the external resistor, R_(DPPM). The output voltage,
V_(OUT), that the DPPM function regulates is V_(DPPM-REG). For example, if R_(DPPM) is 33 kΩ, then the
V_(DPPM-SET)voltage on the DPPM pin is 3.3 V (I_(DPPM-SET) = 100 µA, typical). The DPPM function attempts to keep
V_(OUT) from dropping below the V_(DPPM-REG) voltage, and is 3.795 V for this example (SF = 1.15, typical).
Figure 5 illustrates DPPM and battery supplement modes as the output current (I_OUT) is increased; channel 1
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