TLC34075 Datasheet, PDF (38/52 Pages) Texas Instruments – Video Interface Palette

3.6 Switching Characteristics (Cont’d.)
TL34075-110, TLC34075-135
PARAMETER
TLC34075-110
TLC34075-135
MIN TYP MAX MIN TYP MAX ^UNIT
SCLK frequency (see Note 10)
85
85 MHz
VCLK frequency
85
85 MHz
ten1 Enable time, RD low to D<0:7> valid
tdis1 Disable time, RD high to D<0:7> disabled
tv1
Valid time, D<0:7> valid after RD high
5
tPLH1
Propagation delay, SFLAG/NFLAG ↑ to SCLK
high (see Note 11)
0
40
17
5
20
0
40 ns
17 ns
ns
20 ns
td1
Delay time, RD low to D<0:7> starting to turn
on
5
5
ns
td2
Delay time, selected input clock high/low to
DOTCLK (internal signal) high/low
7
7
ns
td3
Delay time, DOTCLK high/low to VCLK
high/low
6
6
ns
td4
Delay time, VCLK high/low to SCLK high/low
Delay time, DOTCLK high/low to SCLK
td5
high/low
0
8
5
0
8
5 ns
ns
Delay time, DOTCLK high to IOR/IOG/IOB
td6
active (analog output delay time) (see Note
20
12)
20
ns
td7
Analog output settling time (see Note 13)
Delay time, DOTCLK high to HSYNCOUT and
td8
VSYNCOUT valid
6
3
6 ns
3
ns
tw6 Pulse duration, SCLK high (see Note 11)
tr
Analog output rise time (see Note 14)
Analog output skew
15
55 15
55 ns
2
2
ns
0
2
0
2 ns
NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and
90% levels is less than 4 ns.
11. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
12. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
13. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
14. Measured between 10% and 90% of the full-scale transition.
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