TLC34075 Datasheet, PDF (22/52 Pages) Texas Instruments – Video Interface Palette

MODE
4
5||
6
MUX CONTROL REGISTER BITS^†
5
4
3
2
1
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
DATA BITS PIXEL BUS
PER
PIXEL^‡
WIDTH
8
8
8
16
8
32
24
32
4
16
SCLK
DIVIDE
RATIO^§
1
2
4
1
4
PIXEL
LATCHING
SEQUENCE^¶
1) P<7:0>
1) P<7:0>
2) P<15:8>
1) P<7:0>
2) P<15:8>
3) P<23:16>
4) P<31:24>
1) P<31:8>
NFLAG = 0:
1) P<3:0>
2) P<11:8>
3) P<19:16>
4) P<27:24>
NFLAG = 1:
1) P<7:4>
2) P<15:12>
3) P<23:20>
4) P<31:28>
† _{Bits 6 and 7 are don’t care bits.}
‡ _{This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,}
often referred to as the number of bit planes. This may be color palette address data (Modes 0 – 4 and 6) or DAC data
(mode 5).
§ _{The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per}
bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8
bit planes, 4 pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but must
be written to the output clock selection register.
¶ _{For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are}
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 3 with a 16-bit pixel bus width, the rising edge of SCLK latches all the data
groups, and the pixel clock shifts them out in the order P<3:0>, P<7:4>, P<11:8>, P<15:12>.
# _{Mode 0 is VGA pass-through mode.}
|| _{Mode 5 is true color mode, in which 24 bits of color information are transferred directly from the pixel port to the DACs;}
overlay is implemented with the remaining 8 bits of the pixel bus. The distribution of pixel port data to the DACs is as
follows: P<31:24> are passed to the blue DAC, P<23:16> are passed to the green DAC, and P<15:8> are passed to
the red DAC. P<7:0> are used to generate overlay data; this operation can be disabled by either grounding P<7:0> or
by clearing the read mask (see Section 1.4.5).
Mode 6 is special nibble mode, the only mode in which the pixel bus width is not equal to the actual physical width, in
bits, of the pixel bus. In this mode, the pixel bus is physically 32 bits wide; depending on the value of SFLAG/NFLAG,
either the upper or lower nibble of each of the four physical bytes is selected to comprise the 16 bits of pixel data (equal
to four 4-bit pixels).
NOTE: Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground lowers
power consumption and, thus, is recommended.
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