TLC34075 Datasheet, PDF (24/52 Pages) Texas Instruments – Video Interface Palette

Pixel read mask register:
Palette address register:
Palette holding register:
Test register:
FFh
xxh
xxh
(Pointing to color palette red value)
2.6 Frame Buffer Interface
The TLC34075 provides two clock signals for controlling the frame buffer interface: SCLK and VCLK. SCLK
can be used to clock out data directly from the VRAM shift registers. Split shift register transfer functionality
is also supported. VCLK is used to clock and synchronize control inputs like HSYNC, VSYNC, and BLANK.
The pixel data presented at the inputs is latched at the rising edge of SCLK in normal mode or the rising edge
of CLK0 in VGA pass-through mode. Control inputs HSYNC, VSYNC, and BLANK are sampled and latched
at the falling edge of VCLK in normal mode, while HSYNC, VSYNC, and VGABLANK are latched at the rising
edge of CLK0 in VGA pass-through mode. Both data and control signals are lined up at the DAC outputs
to the monitors through the internal pipeline delay, so external glue logic is not required. The outputs of the
DACs are capable of directly driving a 37.5-Ω load, as in the case of a doubly terminated 75-Ω cable. See
Figures 9 and 10 for nominal output levels.
2.7 Analog Output Specifications
The DAC outputs are controlled by current sources (three for IOG and two each for IOR and IOB) as shown
in Figure 8. In the normal case, there is a 7.5-IRE difference between blank and black levels, which is shown
in Figure 9. If a 0-IRE pedestal is desired, it can be selected by resetting bit 4 of the general control register
(see Section 2.11.3). The video output for a 0-IRE pedestal is shown in Figure 10.
VAA
SYNC
(IOG Only)
BLANK
G <0:7>
IOG
∼ 15 pF
RL
Figure 8. Equivalent Circuit of the IOG Current Output
2–12