TLC34075 Datasheet, PDF (11/52 Pages) Texas Instruments – Video Interface Palette

1.5 Terminal Functions
PIN NAME
NO.
I/O
BLANK,
60, 61
I
VGABLANK
CLK<0:2>
77, 76, 75 I
CLK3, CLK3
74, 73
I
COMP
52
I
D<0:7>
36 – 43
I/O
FS ADJUST
51
I
GND
44, 54,
56, 80
HSYNCOUT,
46, 47
O
VSYNCOUT
HSYNC, VSYNC 58, 59
I
IOR, IOG, IOB 48, 49, 50 O
MUXOUT
63
O
P<0:31>
RD
RS<0:3>
SCLK
29 –1,
I
84 – 82
31
I
32–35
I
79
O
DESCRIPTION
Blanking inputs. Two blanking inputs are provided in order to remove any
external multiplexing of the signals that may cause data and blank to skew.
When the VGA pass-through mode is set in the mux control register, the
VGABLANK input is used for blanking; otherwise, BLANK is used.
Dot clock inputs. Any of the three clocks can be used to drive the dot clock
at frequencies up to 85 MHz. When VGA pass-through mode is active, CLK0
is used by default.
Dual-mode dot clock input. This input is an ECL-compatible input, but a TTL
clock may be used on either CLK3 or CLK3 if so selected in the input clock
selection register. This input may be selected as the dot clock for any
frequency of operation up to the device limit while in the ECL mode; it may only
be used up to 85 MHz in the TTL mode.
Compensation input. This terminal provides compensation for the internal
reference amplifier. A resistor and ceramic capacitor are required between
this terminal and VDD. The resistor and capacitor must be as close to the
device as possible to avoid noise pickup. Refer to Appendix B for more
details.
MPU interface data bus. Used to transfer data in and out of the register map
and palette/overlay RAM.
Full-scale adjustment pin. A resistor connected between this pin and ground
controls the full-scale range of the DACs.
Ground. All GND pins must be connected. The analog and digital GND pins
are connected internally.
Horizontal and vertical sync outputs of the true/complement gate mentioned
in the HSYNC, VSYNC description below (see Section 2.8).
Horizontal and vertical sync inputs. These signals are used to generate the
sync level on the green current output. They are active-low inputs for the
normal modes and are passed through a true/complement gate. For the VGA
pass-through mode, they are passed through to HSYNCOUT and
VSYNCOUT without polarity change as specified by the control register (see
Section 2.8).
Analog current outputs. These outputs can drive a 37.5-Ω load directly
(doubly terminated 75-Ω line), thus eliminating the need for any external
buffering.
MUX output control. This output pin is software programmable. It is set low
to indicate to external devices that VGA pass-through mode is being used
when the MUX control register value is set to 2Dh. If bit 7 of the general control
register is set high after the mode is set, this output goes high. This pin is only
used for external control; it affects no internal circuitry.
Pixel input port. This port can be used in various modes as shown in the MUX
control register. It is recommended that unused pins be tied to ground to lower
the device’s power consumption.
Read strobe input. A low logic level on this pin initiates a read from the
TLC34075 register map. Reads are performed asynchronously and are
initiated on the falling edge of RD (see Figure 3 –1).
Register select inputs. These pins specify the location in the register map that
is to be accessed, as shown in Table 2–1.
Shift clock output. This output is selected as a submultiple of the dot clock
input. SCLK is gated off during blanking.
1–5