TLC34075 Datasheet, PDF (19/52 Pages) Texas Instruments – Video Interface Palette

NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low
if the SSRT function is enabled (general control register bit 2 = 1).
VCLK
BLANK
at Input Pin
SFLAG/NFLAG
LOAD
(Internal Signal
for Data Latch)
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
BLANK
(Internal Signal
Before DOTCLK
Pipeline Delay)
PIXEL DATA
at Input Pin
SCLK
Last
Group
3rd
5th
2nd Group 4th _Group 6th
Group
Group
Group
1st Group of Pixel Data
SCLK Between Split Shift Register
and Regular Shift Register Transfer
Figure 7. SCLK/VCLK Control Timing (SSRT Enabled,
SCLK Frequency = 4 × VCLK Frequency)
2.4 Multiplexing Scheme
The TLC34075 offers a highly versatile multiplexing scheme as illustrated in Table 6. The on-chip
multiplexing allows the system to be reconfigured to the amount of RAM available. For example, if only
256K bytes of memory are available, an 800-by-600 mode with 4 bit planes (four bits per pixel) could be
implemented using an 8-bit-wide pixel bus. If, at a later date, another 256K bytes are added to another eight
bits of the pixel bus, the user has the option of using 8 bit planes at the same resolution or 4 bit planes at
a 1024-by-768 resolution. When an additional 512K bytes is added to the remaining 16 bits of the pixel bus,
the user has the option of 8 bit planes at 1024-by-768 or 4 bit planes at 1280 by 1024. All the above can
be achieved without any hardware modification and without any increase in the speed of the pixel bus.
2.4.1 VGA Pass-Through Mode
Mode 0, the VGA pass-through mode, is used to emulate the VGA modes of most personal computers. The
advantage of this mode is that the TLC34075 can take data presented on the feature connectors of most
VGA-compatible PC systems into the device on a separate bus, thus requiring no external multiplexing. This
feature is particularly useful for systems in which the existing graphics circuitry is on the motherboard. In
this instance, it enables implementation of a drop-in graphics card that maintains compatibility with all
existing software by using the on-board VGA circuitry but routing the emerging bit-plane data through the
TLC34075. This is the default mode at power-up. When the VGA pass-through mode is selected after the
device is powered up, the clock selection register, the general control register, and the pixel read mask
register are set to their default states automatically.
Since this mode is designed with the feature connector philosophy, all the timing is referenced to CLK0,
which is used by default for VGA pass-through mode. For all the other normal modes, CLK <0:3> are the
oscillator sources for DOTCLK, VCLK, and SCLK; all the data and control timing is referenced to SCLK.
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