THS1031CPW Datasheet, PDF (35/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
driving the clock input
Obtaining good performance from the THS1031 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at
the CLK input, any clock buffers external to the THS1031 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
The CLK input threshold is nominally around AV_DD/2—ensure that any clock buffers have an appropriate supply
voltage to drive above and below this level.
digital output loading and circuit board layout
The THS1031 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30 MHz clock and 3 V
digital supply. Minimizing the load on the outputs will improve THS1031 signal-to-noise performance by
reducing the switching noise coupling from the THS1031 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buffering the THS1031 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1031 and this buffer.
Noise levels at the output buffers, and hence coupling to the analog circuits within THS1031, becomes worse
as the THS1031 digital supply voltage is increased. Where possible, consider using the lowest DV_DD that the
application can tolerate.
Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1031 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1031 should be soldered directly to the PCB for best performance. Socketing
the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1031
D Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails.
D ORG modes offer the simplest configurations for ADC reference generation.
D Choose differential input mode for best distortion performance.
D Choose a 2-V ADC input span for best noise performance.
D Choose a 1-V ADC input span for best distortion performance.
D If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the
system. Care should be taken to ensure noise is not injected into the THS1031.
D Use external voltage sources for ADC reference generation where there are stringent requirements on
accuracy and drift.
D Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB
traces.
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