THS1031CPW Datasheet, PDF (13/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
The analog input AIN is sampled in the sample-and-hold unit, the output of which goes to a programmable gain
amplifier (PGA). The PGA feeds the ADC core, where the process of analog to digital conversion is performed
against ADC reference voltages, REFTF and REFBF.
Connecting the MODE pin to one of three voltages, AGND, AV_DD or AV_DD/2 sets up operating configurations.
The three settings open or close internal switches to select one of the three basic methods of ADC reference
generation.
Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the
internal reference buffer (IRB) or may be fed from completely external sources. Where the reference buffer is
employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external
voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and
REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user.
The THS1031 offers a clamp function for dc restoration of ac-coupled signals. The clamp voltage may be set
digitally via the 10-bit clamp DAC or by the analog level applied to the CLAMPIN input.
The ADC core drives out through output buffers to the I/O pins I/O0 to I/O9. The output buffers can be disabled
by the OE pin. Control input data on I/O0 to I/O9 can then be written, by pulses on WR, to the control registers.
These registers control clamp operation, output format (unsigned binary or twos complement), the PGA gain
setting and the device power down function.
A single-ended, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is
sampled on the rising edge of CLK, and corresponding data is output after the following third rising edge.
The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1031 can handle.
The following sections explain:
D The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages;
D The ways in which the ADC reference voltages can be buffered internally, or externally applied;
D How to set the onboard reference generator output, if required, and several examples of complete
configurations.
D Subsequent sections explain the clamp function and digital controls, followed by more detailed application
information.
signal processing chain (sample and hold, PGA, ADC)
Figure 11 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
REFTF
AIN
REFTS
REFBS
1
Sample
–1/2 and
–1/2 ^Hold
VP+
VQ+
PGA
VP–
VQ–
ADC
Core
REFBF
Figure 11. Analog Input Signal Flow
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