THS1031CPW Datasheet, PDF (34/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
clamp operation (continued)
Thus if a constant voltage is applied to the clamp input that drives the ADC output to code 1023 (with no
over-range), then the ADC output code will slowly drop to code 1022, or possibly code 1021, over the period
t_d.
If the calculated droop is greater than can be tolerated in the application then increase C_IN to slow the droop
and hence reduce the voltage change between clamp pulses.
If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly
larger than calculated above due to the capacitor’s rapid rate of self-discharge. Avoid using electrolytic and
tantalum coupling capacitors as these usually exhibit much higher leakage then nonpolarized capacitor types.
Electrolytic and tantalum capacitors also tend to have higher parasitics inductance, which can cause further
problems at high input frequencies.
steady-state clamp voltage error
Under steady-state conditions, the change in the clamp voltage caused during clamping must equal the change
caused by clamp droop, otherwise the effect causing the largest voltage change would pull the clamp voltage
away until these charging and droop effects equalize.
Figure 40 shows the approximate voltage waveform at AIN resulting from clamp droop during t_d and clamp
voltage reacquisition during the clamp pulse time, t_c.
V(Clamp)
VCOS
VAIN
VDROOP = ∆VAIN
tc
td
VM
Figure 40. Approximate Waveforms at AIN During Droop and Clamping
The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming
that almost all of V_COS appears across R_IN, giving a charging current V_COS/Rin (this is a reasonable
approximation when V_COS is large enough to be a problem). The voltage change at AIN during clamp acquisition
is then
+ DVAIN
VCOS
RIN
tc
(24)
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the
droop voltage to the clamp acquisition voltage change gives
+ VCOS
RIN IIN
tc
td
(25)
Where I_IN is the input current given by equation, thus for low offset voltage, keep R_IN low and ensure that the
ratio t_d/t_c is not unreasonably large.
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