TMS320DM6443_07 Datasheet, PDF (33/221 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6443
Digital Media System-on-Chip
SPRS282E – DECEMBER 2005 – REVISED MARCH 2007
SIGNAL
NAME
EM_A[1]/
(ALE)/
HHWIL
EM_A[2]/
(CLE)/
HCNTL0
EM_WAIT/
(RDY/BSY)/
IORDY/
HRDY
EM_OE/
(RE)/
(IORD)/
DIOR/
HDS1
EM_WE
(WE)
(IOWR)/
DIOW/
HDS2
EM_CS2/
HCS
EM_CS3
EM_CS4/
GPIO9/
VLYNQ_SCRUN
EM_CS5/
GPIO8/
VLYNQ_CLOCK
Table 2-9. EMIFA Terminal Functions (continued)
TYPE⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD
J2 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA and HPI.
For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).
J1 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA and HPI.
For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).
F1 I/O/Z
IPU
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD, it is ready/busy input (RDY/BSY).
H4 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD, it is read enable output (RE).
G2 I/O/Z
C2 I/O/Z
B1 I/O/Z
T2 I/O/Z
T1 I/O/Z
DV_DD18
This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), ATA/CF, and HPI.
For NAND/SmartMedia/xD, it is write enable output (WE).
DV_DD18
DV_DD18
DV_DD18
DV_DD18
This pin is multiplexed between EMIFA and HPI.
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous
memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot
and ROM boot modes.
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous
memories (i.e. NOR flash) or NAND flash.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip
Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or
NAND flash.
This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip
Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or
NAND flash.
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