TMS320DM6443_07 Datasheet, PDF (139/221 Pages) Texas Instruments – Digital Media System-on-Chip

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EM_CS[5:2]
SETUP
STROBE
TMS320DM6443
Digital Media System-on-Chip
SPRS282E – DECEMBER 2005 – REVISED MARCH 2007
Extended Due to EM_WAIT
STROBE HOLD
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
EM_WAIT
28
25
2
Asserted
2
Deasserted
Figure 6-24. EM_WAIT Write Timing Requirements
6.10.2 DDR2 Memory Controller
The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A
standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM
devices. For details on the DDR2 Memory Controller, see Section 2.8.3, Document Support for the link to
the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literature number SPRUE19) for the
TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUE22).
DDR2 SDRAM plays a key role in a DaVinci-based system. Such a system is expected to require a
significant amount of high-speed external memory for:
• Buffering of input image data from sensors or video sources
• Intermediate buffering for processing/resizing of image data in the VPFE
• Numerous OSD display buffers
• Intermediate buffering for large raw Bayer data image files while performing image processing
functions
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable code for both the ARM and DSP
A memory map of the DDR2 Memory Controller registers is shown in Table 6-36.
Table 6-36. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
0x01C4 004C
0x01C4 2030
0x2000 0000 - 0x2000 0003
0x2000 0004
0x2000 0008
0x2000 000C
0x2000 0010
0x2000 0014
0x2000 0020
0x2000 0024 - 0x2000 00BF
0x2000 00C0
0x2000 00C4
ACRONYM
DDRVTPER
DDRVTPR
-
SDRSTAT
SDBCR
SDRCR
SDTIMR
SDTIMR2
PBBPR
-
IRR
IMR
REGISTER NAME
DDR2 VTP Enable Register
DDR2 VTP Register
Reserved
SDRAM Status Register
SDRAM Bank Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register
SDRAM Timing Register 2
Peripheral Bus Burst Priority Register
Reserved
Interrupt Raw Register
Interrupt Masked Register
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Peripheral and Electrical Specifications 139