TMS320DM6443_07 Datasheet, PDF (157/221 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6443
Digital Media System-on-Chip
SPRS282E – DECEMBER 2005 – REVISED MARCH 2007
6.13 Video Processing Sub-System (VPSS) Overview
The DM6443 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input
interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video
Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital
LCD panels, HDTV video encoders, etc.
Note: The VPSS module is supported with Linux Application Peripheral Interfaces (APIs) commonly used
by video application developers. Video for Linux 2 or V4L2 uses APIs commonly used for video capture.
The typical use cases of the VPSS Video Front-End (VPFE) have been ported to this Linux API structure.
V4L2 supports standard video interfaces such as: BT.656 and Y/C mode. Other modules within the VPSS
VPFE for example, the Preview Engine, H3A, and Histogram are not currently supported within the
software APIs. The VPSS Back-End (VPBE) uses FBDev/DirectFB as the APIs. Certain functionalities
within the VPBE have not been implemented in the FBDev/DirectFB APIs. For modes/functions not
implemented in software, it is the user's responsibility to modify the software drivers/APIs.
The VPSS register memory mapping is shown in Table 6-46.
Table 6-46. VPSS Register Descriptions
HEX ADDRESS
RANGE
0x01C7 3400
0x01C7 3404
0x01C7 3408
0x01C7 3508
0x01C7 350C -
0x01C7 3FFF
REGISTER ACRONYM
PID
PCR
-
SDR_REG_EXP
-
DESCRIPTION
Peripheral Revision and Class Information
VPSS Control Register
Reserved
SDRAM Non Real-Time Read Request Expand
Reserved
To ensure NTSC- and PAL-compliant output video, the stability of the input clock source is very important.
TI recommends a 27-MHz, 50-ppm crystal. Ceramic oscillators are not recommended. The NTSC/PAL
color sub-carrier frequency is derived from the 27-MHz clock. Therefore, if the 27-MHz clock drifts, then
the color sub-carrier frequency will drift as well. Assuming no 27-MHz frequency drift, the color sub-carrier
frequency is generated as follows:
f_{sc -ntsc}
=
27 MHz
çæ ³⁵ ÷ö
è ²⁶⁴ ø
= 3.5795454545
MHz
f_{sc -pal}
=
27 MHz çæ ¹⁶⁷ ÷ö
è ¹⁰¹⁷ ø
=
4.4332628318
MHz
To ensure the color sub-carrier frequency will not drift out of spec, the user must follow the crystal
requirements discussed in Section 6.5.1, Clock Input Option 1 – Crystal or Ceramic Resonator.
6.13.1 Video Processing Front-End (VPFE)
The Video Processing Front-End (VPFE) on the DM6443 consists of the Resizer.
• The Resizer module re-sizes the input image data to the desired display or video encoding resolution
The VPFE register memory mapping is shown in Table 6-47.
Table 6-47. VPFE Register Descriptions
HEX ADDRESS RANGE
0x01C7 0400 – 0x01C7 07FF
0x01C7 0800 – 0x01C7 0BFF
0x01C7 0C00 – 0x01C7 09FF
0x01C7 1000 – 0x01C7 13FF
ACRONYM
RESZ
Reserved
Reserved
VPFE – Resizer
Reserved
REGISTER NAME
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Peripheral and Electrical Specifications 157