TMS320DM6443_07 Datasheet, PDF (169/221 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6443
Digital Media System-on-Chip
SPRS282E – DECEMBER 2005 – REVISED MARCH 2007
Table 6-55. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and VPBECLK⁽¹⁾ (see Figure 6-49)
NO.
PARAMETER
-594
MIN
UNIT
MAX
11
t_{d(PCLK-VCTLV)}
12
t_{d(PCLK-VCTLIV)}
13
t_{d(PCLK-VDATAV)}
14
t_{d(PCLK-VDATAIV)}
29
t_{d(VPBECLK-VCTLV)}
30
t_{d(VPBECLK-VCTLIV)}
31
t_{d(VPBECLK-VDATAV)}
32
t_{d(VPBECLK-VDATAIV)}
Delay time, PCLK edge to VCTL valid
Delay time, PCLK edge to VCTL invalid
Delay time, PCLK edge to VDATA valid
Delay time, PCLK edge to VDATA invalid
Delay time, VPBECLK rising edge to VCTL valid
Delay time, VPBECLK rising edge to VCTL invalid
Delay time, VPBECLK rising edge to VDATA valid
Delay time, VPBECLK rising edge to VDATA invalid
13.3 ns
2
ns
13.3 ns
2
ns
13.3 ns
2
ns
13.3 ns
2
ns
(1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
VCTL^(A)
VDATA^(B)
11, 29
13, 31
12, 30
14, 32
A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-49. VPBE Output Timing With Respect to PCLK and VPBECLK
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Peripheral and Electrical Specifications 169